11/4/2022 0 Comments Analog to digital converter noise![]() ![]() The ADC circuit of claim 1, wherein the selection bounds a difference between a number of times each of the at least two capacitors is set to 1 and a number of times each of the at least two capacitors is set to 0 during previous conversions.Ĥ. The ADC circuit of claim 1, wherein the dither control circuit includes: a digital filter circuit configured to accumulate or process a difference between a number of times the at least two capacitors are set to 1 and a number of times the at least two capacitors are set to 0 during previous conversions and a shuffler circuit coupled to an output of the digital filter circuit, wherein outputs of the shuffler circuit are coupled to the at least two capacitors, the shuffler circuit configured to: receive the dither signal and a signal (“b x”) representing a bit-trial result of a bit-trial phase shuffle the received signals and apply the shuffled signals to the outputs of the shuffler circuit.ģ. An analog-to-digital converter (ADC) circuit to apply noise-shaped dither after a sampling phase, the ADC circuit comprising: a digital-to-analog converter (DAC) circuit having a capacitor array and a dither control circuit configured to control, after the sampling phase, a selection between: at least two capacitors, including: a capacitor in the array to receive a dither signal and a capacitor in the array to be set dependent on a comparator decision during a conversion, wherein, over a number of conversions, the dither control circuit is configured to change the selection of which capacitor receives the dither signal and which capacitor is to be set dependent on a comparator decision during the conversion.Ģ. ![]()
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